.TH E1432_SET_CLOCK_SOURCE 3 E1432
.SH NAME
.nf
e1432_set_clock_source \- Set sample clock source
e1432_get_clock_source \- Get current value of sample clock source
.fi
.IX e1432_set_clock_source(3) 3
.IX e1432_get_clock_source(3) 3
.SH SYNOPSIS
.cS
SHORTSIZ16 e1432_set_clock_source(E1432ID hw, SHORTSIZ16 ID,
                                  SHORTSIZ16 source)
SHORTSIZ16 e1432_get_clock_source(E1432ID hw, SHORTSIZ16 ID,
                                  SHORTSIZ16 *source)
.cE
.SH DESCRIPTION
A typical measurement doesn't generally need to deal with
\fIe1432_set_clock_source\fR at all.  Normally, the call to
\fIe1432_init_measure\fR automatically takes care of setting the clock
source for all the modules in a measurement, by internally calling
\fIe1432_set_clock_source\fR for each module.  This automatic setup
can be disabled using the \fIe1432_set_auto_group_meas\fR function.

\fIe1432_set_clock_source\fR sets the source of the sample clock, of a
single channel or group of channels \fIID\fR, to the value given in
\fIsource\fR.  If a measurement is in progress while calling this
function, the measurement is aborted.

\fIe1432_get_clock_source\fR returns the current value of the sample clock
source, of a single channel or group of channels \fIID\fR,
into a memory location pointed to by \fIsource\fR.

This parameter is a "global" parameter.  It applies to an entire E1432
module rather than to one of its channels.  The \fIID\fR parameter is
used only to identify which module the function applies to, and all
channels in that module will report the same value for this parameter.

\fIhw\fR must be the result of a successful call to
\fIe1432_assign_channel_numbers\fR, and specifies the group of
hardware to talk to.

\fIID\fR is either the ID of a group of channels that was obtained with a
call to \fIe1432_create_channel_group\fR, or the ID of a single channel.

\fIsource\fR determines the source for the sample clock.

\fBE1432_CLOCK_SOURCE_INTERNAL\fR selects the internal sample clock.
This is the default.  With this clock source, the clock frequency
programmed by \fIe1432_set_clock_freq\fR will get rounded to one of
the valid clock frequencies that the E1432 hardware can generate.

\fBE1432_CLOCK_SOURCE_INT_VXI10\fR is nearly the same as
\fBE1432_CLOCK_SOURCE_INTERNAL\fR.  It is different only if the clock
frequency (programmed by \fIe1432_set_clock_freq\fR) is set to one of
the valid clock frequencies that is a sub-multiple of 10 MHz.
Normally when the clock frequency is one of these values, the module
divides down an internal 10 MHz crystal oscillator to produce the
sample clock.  The \fBE1432_CLOCK_SOURCE_INT_VXI10\fR value causes the
module to instead divide down the VXI backplane 10 MHz clock line to
produce the sample clock.  Usually you don't want to do that, because
the internal crystal is more accurate, more stable, and less noisy.
If you switch to the backplane 10 MHz line, the module may not meet
all of its specifications.  But special applications might want to
force the use of the backplane 10 MHz line.

\fBE1432_CLOCK_SOURCE_VXI\fR selects the VXI bus sample clock.  This
assumes that something else out there is producing the sample clock on
one of the VXI TTLTRG lines.  The clock frequency coming in can be
anything within the range of 40960 Hz to 196608 Hz (max 102400 Hz for
E1432, max 196608 Hz for E1433), but the clock frequency coming in
must match the clock frequency told to the module with
\fIe1432_set_clock_freq\fR.  The clock frequency coming in must be a
fixed frequency so that the internal phase locked loop can accurately
lock to this frequency.

\fBE1432_CLOCK_SOURCE_EXTERNAL\fR and
\fBE1432_CLOCK_SOURCE_EXTERNALN\fR select the external sample clock,
positive true and negative true respectively.  The clock frequency
coming in can be anything within the range of 40960 Hz to 196608 Hz
(max 102400 Hz for E1432, max 196608 Hz for E1433, max 65536 for
E1434).  The clock frequency coming in must match the clock frequency
told to the module with \fIe1432_set_clock_freq\fR, and the clock
frequency coming in must be constant so that the module's PLL can lock
to it successfully.

The external sample clock input is present on any E143x module except
those which have the optional 1D4 source board.  This input is an SMB
connector labeled "ExSamp".  The external sample clock input is a TTL
input, so the external clock signal must have TTL signal levels.

To use the external sample clock input, you will need to use
\fIe1432_set_auto_group_meas\fR, and also program the clock master and
multi-sync parameters for all the E143x modules in the measurement.
See \fIe1432_set_auto_group_meas\fR for more information.

\fBE1432_CLOCK_VXI_DEC_3\fR selects the VXI bus clock, divided by 3,
provided by some other clock master.  The \fBE1432_CLOCK_VXI_DEC_3\fR
mode was provided for use with the E1431 module, which generates a
clock that is 196608 Hz, which is three times 65536.  To use the same
clock line for both an E1431 and an E1432, the E1431 must be the clock
master, and the E1432 must use \fBE1432_CLOCK_VXI_DEC_3\fR to get a
clock frequency that it can use.  However, the hardware to implement
this option on the E1432 module has never been tested and the use of
this option is not recommended or supported.

For clock sources external to the module,
\fIe1432_set_clock_frequency\fR must be set to the frequency being
input to the module in order for the internal phase locked loop to be
configured correctly.

Note that if \fIe1432_init_measure\fR is subsequently called and
\fIe1432_set_auto_group_meas\fR has not been set to
\fBE1432_AUTO_GROUP_MEAS_OFF\fR, the clock source will be reset to a
default value.  See \fIe1432_init_measure\fR and
\fIe1432_set_auto_group_meas\fR for more detailed information.

.B Other External Sample Clocks

If you have an E143x module that does not have the external sample
clock connector on the front panel, it may be possible to use the TRIG
IN connector on the front panel of a V/743 or E1482B MXI card to
provide an external sample clock.  Perhaps a VXLink card has this as
well.  In this case, you would use use \fBE1432_CLOCK_SOURCE_VXI\fR
for all E1432 modules in the measurement.

To use the TRIG IN connector on the V/743 or E1482B MXI card would
probably require using some low-level SICL function calls to set it up
correctly.  I haven't actually done this myself, but I believe you use
the ivxitrigroute function to do this with a V/743, and you instead
use the file \fC/usr/pil/etc/vxi16/oride.cf\fR to configure a MXI card
to do this.

In multiple module E1432/E1433 systems, changing the clock source after
a measurement has been made without first resetting the measurement can
result in difficult to diagnose errors.
For this reason, it is advisable to precede each \fIe1432_set_clock_source\fR
call in even potentially multimodule systems with with a
\fIe1432_reset_measure\fR call.

.SH "RESET VALUE"
After a reset, \fIsource\fR is set to \fBE1432_CLOCK_SOURCE_INTERNAL\fR.
.SH "RETURN VALUE"
Return 0 if successful, a (negative) error number otherwise.
.SH "SEE ALSO"
.na
e1432_set_auto_group_meas, e1432_init_measure, e1432_set_clock_freq,
e1432_set_ttltrg_clock
.ad
